Memory systems on system boards are designed to incorporate higher density and faster operation due to the demands of applications that operate on the system boards. Two design techniques that may be employed to incorporate higher density of a memory system on a system board include using serial interconnection configurations such as daisy chain cascading and parallel interconnection configurations such as multi-dropping. These design techniques may be used to overcome density issues that relate to the cost and operating efficiency of memory swapping between a hard disk and a memory system. Multi-dropping has a shortcoming relative to the daisy chain cascading of memory systems. In particular, if the number of devices in a multi-drop memory system increases, delay time increases as a result of a loading effect of each pin. Moreover, the total performance of multi-drop configurations is degraded by wire resistor-capacitor (RC) loading and the pin capacitance of the memory device.
The use of serialized port connections on system boards has become commonplace in electronic products to reduce interference noise and to reduce board implementation size. The device identifier (ID) assignment of a memory device connected in a serial configuration has been performed with additional pin-by-pin connections to Vdd and Vss so that an ID number can be easily assigned to each device on a cascaded chain. However, this approach requires more pins to make a hard-wired ID number on the system board.
U.S. Pat. No. 5,404,460 granted to Thomsen et al. on Apr. 4, 1995 discloses the configuration of multiple identical serial I/O devices connected in a daisy chain fashion on a serial bus and the generation of device numbers. In the configuration, at power-up or reset, the end I/O device configures itself as Device 0 and provides data to the next device to configure as that device as Device 1. Device 1 provides data to configure the next device as Device 2 and so on. As such, all devices in the chain are assigned a device number. Therefore, all devices are configured to unique addresses without additional external pins or intervention by a system controller. The data is transmitted in a six bit packet. The first three bits consist of the start bit and two packet bits which represent command. The following bits are used as ID bits followed by a stop bit. There is an optional bit. Due to the sequential serial stream on a daisy chain, during one cycle, packet command input processing and the generation of a new command for the next device needs to take place within one clock cycle.